27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1351 of 1658
REJ09B0261-0100
27.3.5 Address Register 2 (FLADR2) FLADR2 is a 32-bit readable/writable register that is valid when the ADRCNT2 bit in FLCMDCR is 1. This register specifies the value to be output as an address in command mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
RRRRRRRRRRRRRRRR
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
RRRRRRRR
ADR[7:0]
Bit Bit Name
Initial
Value R/W Description
31 to 8 — All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
7 to 0 ADR[7:0] All 0 R/W Fifth Address Data
Specify the fifth data to be output to flash memory as an
address in command access mode.