19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 872 of 1658
REJ09B0261-0100
19.3.17 Equal Pulse Width Register (EQWR) The equal pulse width register (EQWR) sets the low-level pulse width of a pulse equivalent to the CSYNC signal. The value is retained during power-on reset and manual reset.
R/W:
Internal update:
R/W:
Internal update:
161718192021222324252627282931 30Bit:
Initial value:
RRRRRRRRRRRRRRRR
0000000000000000
R/WR/WR/WR/WR/WR/WR/WRRRRRRRRR
OOOOOOO
000000000
EQW
— —
01234567891011121315 14Bit:
Initial value:
Bit Bit Name
Initial
Value R/W
Internal
Update Description
31 to 7 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
6 to 0 EQW Undefined R/W Yes Equal Pulse Width
The low-level pulse width of a pulse equivalent
to the CSYNC signal should be set in dot clock
units.
To enable this setting, bit 1 of the CSY bits in
DSMR should be set to 1.