16. Watchdog Timer and Reset (WDT)
Rev.1.00 Jan. 10, 2008 Page 768 of 1658
REJ09B0261-0100
16.3.5 Watchdog Timer Base Counter (WDTBCNT) WDTBCNT is a 32-bit read-only register comprising an 18-bit counter that is incremented by the peripheral clock (Pck). When WDTBCNT overflows, WDTCNT is incremented and WDTBCNT is cleared to H'0000 0000. WDTBCNT is only reset by a power-on reset. Writing to this register is invalid.
161718192021222324252627282931 30
0000000000000000
WDTBCNT
⎯⎯
RRRRRRRRRRRRRRRR
Bit:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
WDTBCNT
RRRRRRRRRRRRRRRR
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 18 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
17 to 0 WDTBCNT All 0 R Base counter value