20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 983 of 1658
REJ09B0261-0100
20.3.5 GA Interrupt Enable Register (GACIER) GACIER is in the GDTA common register block and sets interrupt output for each module.
161718192021222324252627282931 30
0000000000000000
⎯⎯
⎯⎯
BIt:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
CL_
ENEN
MC_
ENEN
CL_
EREN
MC_
EREN
⎯⎯
R/WR/WR/WR/W⎯⎯
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 4 All 0 Reserved
These bits are always read as 0. The write value should
always be 0.
3 MC_EREN 0 R/W Controls output of an MC module error interrupt
0: Does not output the interrupt.
1: Outputs the interrupt.
2 CL_EREN 0 R/W Controls output of a CL module error interrupt
0: Does not output the interrupt.
1: Outputs the interrupt.
1 MC_ENEN 0 R/W Controls output of an MC module processing end
interrupt
0: Does not output the interrupt.
1: Outputs the interrupt.
0 CL_ENEN 0 R/W Controls output of a CL module processing end interrupt
0: Does not output the interrupt.
1: Outputs the interrupt.