13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 624 of 1658
REJ09B0261-0100
(24) PCI Cache Snoop Control Register 0 (PCICSCR0) An external PCI device can access memory of this LSI via the PCIC. When an PCI device accesses a cacheable area, the PCIC can issue cache snoop commands to the on-chip caches. This register can specify the function that uses PCICSAR0. For details, see section 13.4.4 (7), Cache Coherency.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
161718192021222324252627282931 30Bit:
Initial value:
R/WR/WR/WR/W
0000000000000000
SNPMDRANGE
R/WRRRRRRRRRRR
RRRRRRRRRRRRRRR R
0000000000000000
— —
——
——
01234567891011121315 14Bit:
Initial value:
Bit Bit Name
Initial
Value R/W Description
31 to 5 All 0 SH: R
PCI: —
Reserved
These bits are always read as 0. The write value
should always be 0.
4 to 2 RANGE All 0 SH: R/W
PCI: —
Address Range to be Compared
These bits specify the address range of PCICSAR0 to
be compared.
000: Compared with PCICSAR0.CADR[31:12] (4 kbytes)
001: Compared with PCICSAR0.CADR[31:16] (64 kbytes)
010: Compared with PCICSAR0.CADR[31:20] (1 Mbyte)
011: Compared with PCICSAR0.CADR[31:24] (16 Mbytes)
100: Compared with PCICSAR0.CADR[31:25] (32 Mbytes)
101: Compared with PCICSAR0.CADR[31:26] (64 Mbytes)
110: Compared with PCICSAR0.CADR[31:27] (128 Mbytes)
111: Compared with PCICSAR0.CADR[31:28] (256 Mbytes)
Valid only when PCICSCR0.SNPMD = 10 or 11.