15. Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 745 of 1658
REJ09B0261-0100
15.4.3 Frequency Display Register 1 (FRQMR1) FRQMR1 is a 32-bit readable register that reads the division ratio of divider 2 for the CPU clock (lck), the SuperHyway clock (SHck), the peripheral clock (Pck), the DDR clock (DDRck),the bus clock (Bck), the GDTA clock (GAck), the DU clock (DUck), and the RAM clock (Uck). FRQMR1 can only be accessed in longwords. This register is initialized by only a power-on reset via the PRESET pin or a WDT overflow.
161718192021222324252627282931 30
1xxxx100x1001000
BFST0BFST1BFST2BFST3SFST0SFST1SFST2SFST3UFST0UFST1UFST2UFST3IFST0IFST1IFST3 IFST2
RRRRRRRRRRRRRRRR
BIt:
Initial value:
R/W:
01234567891011121315 14
xx01xx1xx010x100
PFST0PFST1PFST2PFST3
S3FST0S3FST1S3FST2S3FST3S2FST0S2FST1S2FST2S2FST3
MFST0MFST1MFST3MFST2
RRRRRRRRRRRRRRRR
BIt:
Initial value:
R/W:
Note: The initial value (x: a bit whose value is undefined) depends on the settings of mode pins MODE0 to MODE4, MODE11, and MODE12 on a power-on reset via the PRESET pin. See Table 15.3 or 15.4.
Bit Bit Name
Initial
Value R/W Description
31
30
29
28
IFST3
IFST2
IFST1
IFST0
0
0
0
1
R
R
R
R
Frequency division ratio of the CPU clock (Ick)
0001: × 1/2
0010: × 1/4
0011: × 1/6
27
26
25
24
UFST3
UFST2
UFST1
UFST0
0
0
1
x
R
R
R
R
Frequency division ratio of the RAM clock (Uck)
0010: × 1/4
0011: × 1/6
23
22
21
20
SFST3
SFST2
SFST1
SFST0
0
0
1
x
R
R
R
R
Frequency division ratio of the SuperHyway clock
(SHck)
0010: × 1/4
0011: × 1/6