16. Watchdog Timer and Reset (WDT)
Rev.1.00 Jan. 10, 2008 Page 764 of 1658
REJ09B0261-0100
16.3.2 Watchdog Timer Control/Status Register (WDTCSR) WDTCSR is a 32-bit readable/writable register comprising timer mode-selecting bits and overflow flags. WDTCSR should be written to as a longword unit, with H'A5 in the most significant byte. The value read from this byte is always H'00. WDTCSR is only rest by a power-on reset caused by the PRESET pin.
161718192021222324252627282931 30
0000000000000000
RRRRRRRRR/WR/WR/WR/WR/WR/WR/W R/W
Bit:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
IOVFWOVFRSTSWT/ITTME
⎯⎯
RRRR/WR/WR/WR/WR/WRRRRRRRR
Bit:
Initial value:
R/W:
Code for writing (H'A5)
Bit Bit Name
Initial
Value R/W Description
31 to 24 (Code for
writing)
All 0 R/W Code for writing (H'A5)
These bits are always read as H'00. When writing to
this register, the value written to these bits must be
H'A5.
23 to 8 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
7 TME 0 R/W Timer Enable
Starts or stops the timer operation.
0: Stops counting up.
1: Starts counting up.
6 WT/IT 0 R/W Timer Mode Select
Specifies whether the WDT is used as a watchdog
timer or interval timer. Up counting may not be
performed correctly if this bit is modified while the
WDT is running.
0: Interval timer mode
1: Watchdog timer mode