14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 674 of 1658 REJ09B0261-0100
Channel Name Abbrev.
Power-on
Reset
by PRESET
Pin/WDT/
H-UDI
Manual
Reset
by
WDT/Multiple
Exception
Sleep
by SLEEP
instruction
Deep Sleep
by SLEEP
instruction
(DSLP = 1)
Module
Standby
9 DMA source address register B9 SARB9 Undefined Undefined Retained Retained Retained
DMA destination address register
B9
DARB9 Undefined Undefined Retained Retained Retained
DMA transfer count register B9 TCRB9 Undefined Undefined Retained Retained Retained
6, 7 DMA extended resource selector 3 DMARS3 H'0000 H'0000 Retained Retained Retained
8, 9 DMA extended resource selector 4 DMARS4 H'0000 H'0000 Retained Retained Retained
10, 11 DMA extended resource selector 5 DMARS5 H'0000 H'0000 Retained Retained Retained