1. Overview
Rev.1.00 Jan. 10, 2008 Page 4 of 1658
REJ09B0261-0100
Item Features
Memory
management
unit (MMU)
4-Gbyte address space, 256 address space identifiers (8-bit ASID)
Supports single virtual memory mode and multiple virtual memory mode
Multiple page sizes: 1, 4, 8, 64, or 256 Kbytes, or 1, 4, or 64 Mbytes
4-entry fully associative TLB for instructions
64-entry fully associative TLB for instructions and operands
Selection of software-driven or random-counter replacement algorithms
The TLB is address-mapped, making its contents directly accessible.
29-bit physical address mode/32-bit extended mode
Cache memory Instruction cache (IC)
32-Kbyte 4-way set associative
256 entries/way, 32-byte block length
Operand cache (OC)
32-Kbyte 4-way set associative
256 entries/way, 32-byte block length
Selectable write method (copy-back or write-through)
Store queue (32 bytes × 2 entries)
One-stage copy-back buffer and one-stage write-through buffer
LRAM ILRAM
8-Kbyte high-speed memory
Three independent read/write ports
8-/16-/32-/64-bit access from the CPU or FPU
8-/16-/32-/64-bit access and 16-/32-byte access in response to
external requests
Support for protection of memory from CPU or FPU access
OLRAM
16-Kbyte high-speed memory
Three independent read/write ports
8-/16-/32-/64-bit access by the CPU or the FPU
8-/16-/32-/64-bit access and 16-/32-byte access in response to
external requests
Support for protection of memory from CPU or FPU access