Renesas SH7781 Figure 32.44 TCK Input Timing

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1605 of 1658
REJ09B0261-0100
32.3.10 H-UDI Module Signal Timing
Table 32.15 H-UDI Module Signal Timing
Conditions: VDDQ= 3.0 to 3.6 V, VDD= 1.1 V, Ta= −40 to 85°C, CL= 30 pF, PLL2 on
Item Symbol Min. Max. Unit Figure Remarks
Input clock cycle tTCKcyc 50 — ns 32.44,
32.46
Input clock pulse width (high) tTCKH 15 — ns 32.44
Input clock pulse width (low) tTCKL 15 — ns
Input clock rise time tTCKr — 10 ns
Input clock fall time tTCKf — 10 ns
ASEBRK setup time tASEBRKS 10 — tcyc 32.45
ASEBRK hold time tASEBRKH 1 — ms
TDI/TMS setup time tTDIS 15 — ns 32.46
TDI/TMS hold time tTDIH 15 — ns
TDO data delay time tTDO 0 12 ns
ASE-PINBRK pulse width tPINBRK 2 — tPcyc 32.47
Notes: 1. Durin g a boundary scan, tTCKcyc is the period corresponding to a frequency of 10 MHz, i.e.
0.1 μs.
2. tcyc is the period of one CKIO clock cycle.
3. tPcyc is the period of one peripheral clock (Pck) cycle.
t
TCKH
t
TCKf
t
TCKr
t
TCKL
t
TCKcyc
V
IH
V
IH
V
IH
1/2V
DDQ
1/2V
DDQ
V
IL
V
IL
Note: When the clock is input from the TCK pin.
Figure 32.44 TCK Input Timing