12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 483 of 1658
REJ09B0261-0100
12.4.2 SDRAM Operation Enable Register (DBEN) The SDRAM operation enable register (DBEN) is a readable/writable register. It is initialized only upon power-on reset.
161718192021222324252627282931 30
0000000000000000
⎯⎯
RRRRRRRRRRRRRRRR
BIt:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
ACEN⎯⎯
R/WRRRRRRRRRRRRRRR
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 1 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
0 ACEN 0 R/W SDRAM Access Enable Bit
By setting this bit, data accessing of SDRAM is enabled.
When set to 0, access is disabled; when set to 1,
access is enabled. When access is disabled, attempts
to access SDRAM are ignored. This bit is used for the
initialization sequence or self-refresh operation.
0: Disables access
1: Enables access