32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1599 of 1658
REJ09B0261-0100
32.3.6 PCIC Module Signal Timing Table 32.11 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (1) Conditions: VDDQ = 3.0 to 3.6 V, VDD = 1.1 V, Ta = –40 to 85°C, CL = 30 pF
33 MHz 66 MHz
Pin Item Symbol Min. Max. Min. Max. Unit Figure
Clock period tPCICYC 30 — 15 30 ns 32.37
Clock pulse width (high) tPCIHIGH 11 — 6 —
Clock pulse width (low) tPCIr 11 — 6 —
Clock rise time tPCIf — 4 — 1.5
PCICLK
Clock fall time tNCDAD1 — 4 — 1.5
PCIRESET Output data delay time tPCIVAL — 10 — 10 ns 32.38
Input setup time tPCISU 3 — 3 — ns 32.39 IDSEL
Input hold time tPCIH 1.5 — 1.5 —
Output data delay time tPCIVAL 2 10 2 6 ns 32.38
Tri-state drive delay time t PCION 2 10 2 6
Tri-state Hi-Z delay time tPCIOFF 2 12 2 6
Input setup time tPCISU 3 — 3 — 32.39
AD31 to AD0,
C/BE3 to C/BE0,
PCIFRAME,
PAR, IRDY,
TRDY, STOP,
LOCK, PERR,
DEVSEL, Input hold time tPCIH 1.5 — 1.5 —
Output data delay time tPCIVAL 2 10 2 6 ns 32.38
Input setup time tPCISU 3 — 3 — 32.39
REQ0/REQOUT,
GNT0/GNTIN
REQ1, REQ2,
REQ3, GNT1,
GNT2, GNT3
Input hold time tPCIH 1.5 — 1.5 —
Tri-state drive delay time t PCION — 10 — 10 ns 32.38
Tri-state Hi-Z delay time tPCIOFF — 12 — 12
SERR, INTA,
INTB, INTC,
INTD Input setup time tPCISU 3 — 3 — 32.39
Input hold time tPCIH 1.5 — 1.5 —