12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 500 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
0 SRFEN 0 R/W Self-Refresh Mode Bit
Performs transition to or cancellation of self-refresh
mode. By writing 1, a transition is made to self-refresh.
By writing 0, self-refresh mode is cancelled. For details
on transition to or cancellation of self-refresh, refer to
section 12.5.4, Self-Refresh Operation.
0: Cancels self-refresh.
1: Makes a transition to self-refresh.
12.4.9 SDRAM Refresh Control Register 1 (DBRFCNT1) The SDRAM refresh control register 1 (DBRFCNT1) is a readable/writable register. It is initialized only upon power-on reset.
161718192021222324252627282931 30
0000000000000000
⎯⎯
RRRRRRRRRRRRRRRR
BIt:
Initial value:
R/W:
01234567891011121315 14
0000000001000000
TREFI0TREFI1TREFI2TREFI3TREFI4TREFI5TREFI6TREFI7TREFI8TREFI9TREFI10TREFI11TREFI12
⎯⎯
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WRRR
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 13 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.