Renesas SH7781 - page 540

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 510 of 1658
REJ09B0261-0100
12.4.14 SDRAM Mode Setting Register (DBMRCNT)
The SDRAM mode setting register (DBMRCNT) is a write-only register. If it is read, correct
operation cannot be guaranteed.
161718192021222324252627282931 30
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
BA0BA1BA2 ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
WWWWWWWWWWWWWWWW
BIt:
Initial value:
R/W:
01234567891011121315 14
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
MA0MA1MA2MA3MA4MA5MA6MA7MA8MA9MA10MA11MA12MA13 ⎯ MA14
WWWWWWWWWWWWWWWW
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 19 ⎯ Undefined W Reserved
These bits are always read as 0. The write value should
always be 0.
If a value other than 0 is written, correct operation
cannot be guaranteed.
18 to 16 BA2 to BA0 Undefined W SDRAM Mode Register and Extended Mode Register
Setting Bits
Bank address pins MBA2, MBA1, and MBA0
correspond to bit 18, bit 17, and bit 16, respectively.
15 ⎯ Undefined W Reserved
This bit is always read as 0. The write value should
always be 0.
If a value other than 0 is written, correct operation
cannot be guaranteed.
14 to 0 MA14 to
MA0
Undefined W SDRAM Mode Register and Extended Mode Register
Setting Bits
The address pins MA14, MA13, ..., and MA0
correspond to bit 14, bit 13, ..., and bit 0, respectively.