Renesas SH7781 8.2 Register Descriptions

8. Caches
Rev.1.00 Jan. 10, 2008 Page 215 of 1658
REJ09B0261-0100
8.2 Register Descriptions
The following registers are related to cache.
Table 8.3 Register Configuration
Register Name Abbreviation R/W P4 Address* Area 7 Address* Size
Cache control register CCR R/W H'FF00 001C H'1F00 001C 32
Queue address control register 0 QACR0 R/W H'FF00 0038 H'1F00 0038 32
Queue address control register 1 QACR1 R/W H'FF00 003C H'1F00 003C 32
On-chip memory control register RAMCR R/W H'FF00 0074 H'1F00 0074 32
Note: * These P4 ad dresses are for the P4 area in the virtual address space. These area 7
addresses are accessed from area 7 in the physical address space by means of the
TLB.
Table 8.4 Register States in Each Processing State
Register Name Abbreviation Power-on Reset Manual Reset Sleep Standby
Cache control register CCR H'0000 0000 H'0000 0000 Retained Retained
Queue address control register 0 QACR0 Undefined Undefined Retained Retained
Queue address control register 1 QACR1 Undefined Undefined Retained Retained
On-chip memory control register RAMCR H'0000 0000 H'0000 0000 Retained Retained