32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1593 of 1658
REJ09B0261-0100
Item Symbol Min. Max. Unit Figure Notes
Write command to first
MDQS delay time
(Rising edge)
tWDQSS WL
0.18
WL
+0.18
tMCK
MDQS falling edge
setup time to MCK
rising edge (Write)
tWDSS 0.27 tMCK
MDQS falling edge hold
time to MCK rising edge
(Write)
tWDSH 0.27 tMCK
MDQS high-level pulse
width (Write)
tWDQSH 0.35 0.9 tMCK
MDQS low-level pulse
width (Write)
tWDQSL 0.35 0.9 tMCK
MDQS preamble (Write) tWPRE 0.35 tMCK
MDQS postamble
(write)
tWPST 0.4 tMCK
430 DDR2-600 MDQ/MDM setup time
to MDQS (Write)
tWDS
630 —
ps
DDR2-400
430 DDR2-600 MDQ/MDM hold time to
MDQS (Write)
tWDH
630 —
ps
DDR2-400
MDQ/MDM signal width
(Write)
tWDIPW 0.35 tMCK
MDQ high-impedance
time from MDQS (Write)
tHZ t
WDH tMCK ns
Note: tMCK: one MCK cycle time
t
CK
t
CH
t
CL
MCK0, MCK1
MCK0, MCK1
Figure 32.26 MCK Output Clock