32. Electrical Characteristics

Rev.1.00 Jan. 10, 2008 Page 1594 of 1658

REJ09B0261-0100

MCK0, MCK1 (solid line)
MCK0, MCK1 (dotted line)
tIH
MCKE, MCS,
MRAS, MCAS,
MWE, MBA[2:0],
MA[14:0]
tIS
tIPW
Figure 32.27 Command Signal and MCK Output Clock
MCK0, MCK1 (solid line)
MCK0, MCK1 (dotted line)
MCKE, MCS,
MRAS, MCAS,
MWE, MBA[2:0],
MA[14:0]
READ
Command
MDQS[3:0] (solid line)
MDQS[3:0] (dotted line)
tRDQSCK (Min.)
MDQS[3:0] (solid line)
MDQS[3:0] (dotted line)
tRDQSCK (Max.)
tRDQSCK (min)
tRDQSCK (min)
tRDQSCK (max)
tRDQSCK (max)
CL (Cas Latency)
Figure 32.28 MDQS Input Timing at Data Read