13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 628 of 1658
REJ09B0261-0100
(27) PCI Cache Snoop Address Register 1 (PCICSAR1) This register specifies the address to be compared with the PCI address requested by an external PCI device to the PCIC. For details, see section 13.4.4 (7), Cache Coherency.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
161718192021222324252627282931 30Bit:
Initial value: 0000000000000000
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/W
CADR
0000000000000000
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/W
CADR
01234567891011121315 14Bit:
Initial value:
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/W R/WR/W
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/W R/WR/W
Bit Bit Name
Initial
Value R/W Description
31 to 0 CADR H'0000
0000
SH: R/W
PCI: R/W
Address to be Compared
This register specifies the address to be compared
with the SuperHyway bus address that is requested
by an external device to the PCI