19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 923 of 1658
REJ09B0261-0100
19.3.53 Output Signal Timing Adjustment Register (OTAR) The output signal timing adjustment register (OTAR) selects the timing for the output signal. For information on adjustment timing, refer to section 19.5.5, Output Signal Timing Adjustment.
R/W:
Internal update:
R/W:
Internal update:
161718192021222324252627282931 30Bit:
Initial value:
RRRRR/WR/WR/WRR/WR/WR/WRR/WR/WR R/W
0000000000000000
DRGBA
CLAMPA
DEA
R/WR/WR/WRR/WR/WR/WRR/WR/WR/WRRRRR
0000000000000000
SYNCA
DISPA
CDEA
— —
01234567891011121315 14Bit:
Initial value:
Bit Bit Name
Initial
Value R/W
Internal
Update Description
31 0 R Reserved
This bit is always read as 0. The write value
should always be 0.