Appendix
Rev.1.00 Jan. 10, 2008 Page 1638 of 1658
REJ09B0261-0100
Reset
Pin Name
(LSI level)
Pin Name
(Module level)
Related
Module I/O
Power
-on Manual Sleep
Module
Standby
Bus
Release
MDOE9 (power-
on reset)
LBSC I I
Port N2 (default) GPIO I/O K K K
SCIF4_TXD SCIF O Z O O O
MDOE9/
SCIF4_TXD/
FD1
FD1 FLCTL I/O K K K K
MODE10
(power-on reset)
CPG I I
Port N1 (default) GPIO I/O K K K
MODE10/
SCIF4_RXD/
FD2
SCIF4_RXD SCIF I I I I I
FD2 FLCTL I/O K K K K
MODE11
(power-on reset)
LBSC I I
Port N0 (default) GPIO I/O K K K
SCIF4_SCK SCIF I/O I K K K
MODE11/
SCIF4_SCK/
FD3
FD3 FLCTL I/O
K K K K
MODE12
(power-on reset)
LBSC I I
Port L0 (default) GPIO I/O K K K
DRAK3 DMAC O O O O O
MODE12/
DRAK3/
CE2B
CE2B LBSC O
K K K K
MODE13 MMU I I
Port J0 (default) GPIO I/O K K K
TCLK TMU I I I I I
MODE13(power-
on reset)/
TCLK/
IOIS16
IOIS16 LBSC I
K K K K
MODE14 MODE14 CPG I I I I I I
EXTAL EXTAL CPG I I I I I
XTAL XTAL CPG O O O O O
Port H4 (default) GPIO I/O PI K K K
SCIF0_CTS SCIF I/O I K K K
SCIF0_CTS/
INTD/
FCE INTD PCIC I
K K K
FCE FLCTL O O K K K