20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 1003 of 1658
REJ09B0261-0100
20.3.22 MC Status Register (MCSR) MCSR is in the MC register block and indicates the internal states of the MC.
161718192021222324252627282931 30
0000000000000000
⎯⎯
⎯⎯
BIt:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
MC_CFS
MC_CFF
MC_CFA
⎯⎯
RRRRRRR⎯⎯
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 11 All 0 Reserved
These bits are always read as 0. The write value should
always be 0.
10 to 8 MC_CFA All 0 R Indicates the number of commands accumulated in
MCCF (command FIFO); maximum number accumulated
is 4
Number of accumulated commands:
000: 0
001: 1
010: 2
011: 3
100: 4
7 to 4 All 0 Reserved
These bits are always read as 0. The write value should
always be 0.
3 MC_CFF 0 R MCCF status display
Indicates the state of command buffer reception.
0: Command receivable
1: Command buffer full