32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1572 of 1658
REJ09B0261-0100
t
MDRH
PRESET
MODE13 to MODE11
MODE8 to MODE5
t
MDRS
t
PRr
t
PRf
Figure 32.6 MODE Pin Setup/Hold Timing 32.3.2 Control Signal Timing Table 32.7 Control Signal Timing Conditions: VDDQ = 3.0 to 3.6 V, VDD = 1.1 V, Ta = 20 to +85/40 to +85°C, CL = 30 pF
Item Symbol Min. Max. Unit Figure
BREQ setup time* t
BREQS 3 ns
BREQ hold time tBREQH 1.5 — ns
BREQ delay time tBACKD — 6 ns
Bus tri-state delay time tBOFF1 — 12 ns
Bus buffer on time tBON1 — 12 ns
32.7
STATUS0, STATUS1 delay time tSTD6 ns 32.8
Note: * t
cyc is the period of one CLKOUT cycle.