Rev.1.00 Jan. 10, 2008 Page xiv of xxx
REJ09B0261-0100
10.4 Interrupt Sources................................................................................................................324
10.4.1 NMI Interrupts.................................................................................................... 324
10.4.2 IRQ Interrupts.....................................................................................................324
10.4.3 IRL Interrupts..................................................................................................... 325
10.4.4 On-Chip Peripheral Module Interrupts............................................................... 327
10.4.5 Priority of On-Chip Peripheral Module Interrupts..............................................328
10.4.6 Interrupt Exception Handling and Priority......................................................... 329
10.5 Operation........................................................................................................................... 337
10.5.1 Interrupt Sequence.............................................................................................. 337
10.5.2 Multiple Interrupts.............................................................................................. 339
10.5.3 Interrupt Masking by MAI Bit............................................................................339
10.6 Interrupt Response Time....................................................................................................340
10.7 Usage Notes....................................................................................................................... 343
10.7.1 Example of Handing Routine of IRL Interrupts and Level Detection
IRQ Interrupts when ICR0.LVLMODE = 0....................................................... 343
10.7.2 Notes on Setting IRQ/IRL[7:0] Pin Function..................................................... 344
10.7.3 Clearing IRQ and IRL Interrupt Requests.......................................................... 345
Section 11 Local Bus State Controller (LBSC)........................................................... 347
11.1 Features..............................................................................................................................347
11.2 Input/Output Pins...............................................................................................................350
11.3 Overview of Areas............................................................................................................. 354
11.3.1 Space Divisions.................................................................................................. 354
11.3.2 Memory Bus Width............................................................................................ 357
11.3.3 PCMCIA Support............................................................................................... 358
11.4 Register Descriptions......................................................................................................... 362
11.4.1 Memory Address Map Select Register (MMSELR)...........................................364
11.4.2 Bus Control Register (BCR)............................................................................... 367
11.4.3 CSn Bus Control Register (CSnBCR)................................................................ 371
11.4.4 CSn Wait Control Register (CSnWCR)..............................................................377
11.4.5 CSn PCMCIA Control Register (CSnPCR)........................................................382
11.5 Operation........................................................................................................................... 387
11.5.1 Endian/Access Size and Data Alignment........................................................... 387
11.5.2 Areas...................................................................................................................398
11.5.3 SRAM interface.................................................................................................. 403
11.5.4 Burst ROM Interface.......................................................................................... 412
11.5.5 PCMCIA Interface..............................................................................................416
11.5.6 MPX Interface.................................................................................................... 427
11.5.7 Byte Control SRAM Interface............................................................................ 441
11.5.8 Wait Cycles between Access Cycles.................................................................. 446