Renesas SH7781 - page 537

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 507 of 1658
REJ09B0261-0100
12.4.13 DDRPAD DIC, ODT, OCD Setting Register (DBDICODTOCD)
The SDRAM refresh status register (DBRFSTS) is a readable/writable register. It is initialized
only upon power-on reset.
161718192021222324252627282931 30
0000000000000000
DICDIC_CKDIC_DQDIC_AD ⎯⎯⎯⎯ DDRSIG ⎯⎯⎯⎯⎯⎯⎯
R/WR/WR/WR/WRRRRR/WRRRRRRR
BIt:
Initial value:
R/W:
01234567891011121315 14
1110000000000000
⎯⎯⎯⎯⎯⎯⎯⎯
T_ODT0T_ODT1
ODT_
EARLY
ODTEN0ODTEN1 ⎯⎯⎯
R/WR/WR/WRRRRRR/WR/WR/WR/WR/WRRR
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 25 ⎯ All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
24 DDRSIG 0 R/W Write Preamble Time Setting Bit
Sets the preamble time of the DQS signal to be output
when data is written to the DDR2-SDRAM. The number
of cycles is the number of DDR clock cycles.
0: Write preamble time = 0.5 cycle
1: Write preamble time = 1 cycle
23 to 20 ⎯ All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
19 DIC_AD 0 R/W Address and Command Pin Impedance Value
This bit should be set to the same value as the value set
for DIC of EMRS(1) in the DDR2-SDRAM.
0: Normal
1: Weak