32. Electrical Characteristics

Rev.1.00 Jan. 10, 2008 Page 1590 of 1658

REJ09B0261-0100

A25 to A0
D31 to D0
(Read)
(SA: IO memory)
Legend:
IO: DACK device
SA: Single-address DMA transfer
DA: Dual-address DMA transfer
Note: DACK is configured as active-high.
T1 Tw T2
t
DACD
t
DACD
t
CSD
t
CSD
t
DACD
t
RDYH
t
RDYS
t
DACD
t
DACD
t
RWD
t
RWD
T1 T2
t
DACD
t
DACD
t
CSD
t
CSD
t
DACD
t
DACD
t
WED1
t
DACD
t
RWD
t
RWD
t
RDYH
t
RDYS
t
RDYH
t
RDYS
t
AD
t
AD
t
AD
t
AD
T1 Tw Twe T2
t
DACD
t
DACD
t
RSD
t
RSD
t
RSD
t
RSD
t
RSD
t
RSD
t
RSD
t
RSD
t
WED1
t
WED1
t
WEDF
t
WED1
t
WEDF
t
WED1
t
WEDF
t
WED1
t
CSD
t
CSD
t
DACD
t
BSD
t
BSD
t
BSD
t
BSD
t
BSD
t
BSD
t
DACD
t
DACD
t
RWD
t
RWD
t
RSD
t
AD
t
AD
t
RDH
t
RDS
t
RDH
t
RDS
t
RDH
t
RDS
CLKOUT
RD
RD/WR
WEn
RDY
BS
CSn
DACKn
(DA)
DACKn
(1) Basic read cycle (no wait) (2) Basic read cycle (one internal wait cycle) (3) Basic read cycle (one internal wait + one external wait cycles)

t

Figure 32.24 Memory Byte Control SRAM Bus Cycle