12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 488 of 1658
REJ09B0261-0100
12.4.5 SDRAM Timing Register 0 (DBTR0) The SDRAM timing register 0 (DBTR0) is a readable/writable register. It is initialized only upon power-on reset.
161718192021222324252627282931 30
1100000001000000
TRAS0TRAS1TRAS2TRAS3
CL0CL1CL2
⎯⎯
R/WR/WR/WR/WRRRRR/WR/WR/WRRRRR
BIt:
Initial value:
R/W:
01234567891011121315 14
1000000010100000
TRCD0TRCD1TRCD2
TRFC0TRFC1TRFC2TRFC3TRFC4TRFC5
TRFC6
R/WR/WR/WRRRRRR/WR/WR/WR/WR/WR/WR R/W
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 27 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
26 to 24 CL2 to CL0 010 R/W CAS Latency Setting Bits
These bits set the CAS latency. These bits should be
set according to the DDR2-SDRAM specifications. The
number of cycles is the number of DDR clock cycles.
When using the ODT (On Die Termination) enable
output signal MODT, these bits should be set to 4 or
more cycles.
000: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
001: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
010: 2 cycles
011: 3 cycles
100: 4 cycles
101: 5 cycles
110: 6 cycles
111: Setting prohibit (If specified, correct operation
cannot be guaranteed.)