12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 495 of 1658
REJ09B0261-0100
12.4.7 SDRAM Timing Register 2 (DBTR2) The SDRAM timing register 2 (DBTR2) is a readable/writable register. It is initialized only upon power-on reset.
161718192021222324252627282931 30
0010000010000000
TRC0TRC1TRC2TRC3TRC4
TRTP0TRTP1
⎯⎯
R/WR/WR/WR/WR/WRRRR/WR/WRRRRRR
BIt:
Initial value:
R/W:
01234567891011121315 14
1100000011000000
WRRD0WRRD1WRRD2WRRD3
RDWR0RDWR1RDWR2RDWR3
⎯⎯
R/WR/WR/WR/WRRRRR/WR/WR/WR/WRRRR
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 26 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
25, 24 TRTP1 and
TRTP0
01 R/W tRTP (READ-PRE command minimum time) Setting Bits
These bits set the READ-PRE command minimum time
constraint for the same bank. These bits should be set
according to the SDRAM specifications. The number of
cycles is the number of DDR clock cycles.
00: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
01: 2 cycles
10: 3 cycles
11: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
23 to 21 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.