10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 277 of 1658
REJ09B0261-0100
10.3.1 External Interrupt Request Registers (1) Interrupt Control Register 0 (ICR0) ICR0 is a 32-bit readable and partially writable register that sets the input signal detection mode for the external interrupt input pins and NMI pin, and indicates the level being input on the NMI pin.
161718192021222324252627282931 30
00000000000000—0
LVL
MODE
IRLM1IRLM0
NMIENMIB
NMIL MAI
RRRRRR/WR/WR/WR/WR/WRRRRR R/W
Bit:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
⎯⎯
RRRRRRRRRRRRRRRR
Bit:
Initial value:
R/W:
Bit Name
Initial
Value R/W Description
31 NMIL Undefined R NMI Input Level
Indicates the signal level being input on the NMI pin.
Reading this bit allows the user to know the NMI pin
level, and writing is invalid.
0: Low level is being input on the NMI pin
1: High level is being input on the NMI pin
30 MAI 0 R/W MAI (mask all interrupts) Interrupt Mask
Specifies whether all interrupts are masked while the
NMI pin is at the low level regardless of the setting of
the BL bit in SR of the CPU.
0: Interrupts remain enabled even when the NMI pin
goes low
1: Interrupts are disabled when the NMI pin goes low
29 to 26 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.