Appendix
Rev.1.00 Jan. 10, 2008 Page 1637 of 1658
REJ09B0261-0100
Reset
Pin Name
(LSI level)
Pin Name
(Module level)
Related
Module I/O
Power
-on Manual Sleep
Module
Standby
Bus
Release
MODE2 (power-
on reset)
CPG I I
Port L2 (default) GPIO I/O K K K
MODE2/
IRQ/IRL6/
FD6
IRQ/IRL6 INTC I I I I
FD6 FLCTL I/O K K K K
MODE3
(POWER-ON
RESET)
CPG I/O I
Port L1 (default) GPIO I/O K K K
IRQ/IRL7 INTC I I I I
MODE3/
IRQ/IRL7/
FD7
FD7 FLCTL I/O
K K K K
MODE4 (power-
on reset)
CPG I I
Port N5 (default) GPIO I/O K K K
SCIF3_TXD SCIF O Z O O O
MODE4/
SCIF3_TXD/
FCLE
FCLE FLCTL O
K K K K
MODE5 (power-
on reset)
LBSC I I MODE5/
SIOF_MCLK
SIOF_MCLK
(default)
SIOF I I I I I
MODE6 (power-
on reset)
LBSC I I MODE6/
SIOF_SYNC
SIOF_SYNC
(default)
SIOF I/O O*2 K K K
MODE7 (power-
on reset)
LBSC I I
Port N4 (default) GPIO I/O K K K
SCIF3_RXD SCIF I I I I I
MODE7/
SCIF3_RXD/
FALE
FALE FLCTL O
K K K K
MODE8 (power-
on reset)
LBSC I I
Port N3 (default) GPIO I/O K K K
MODE8/
SCIF3_SCK/
FD0
SCIF3_SCK SCIF I/O
I K K K
FD0 FLCTL I/O K K K K