Renesas SH7781 - page 23

Rev.1.00 Jan. 10, 2008 Page xxiii of xxx
REJ09B0261-0100
21.3.12 Serial Port Register n (SCSPTR)...................................................................... 1066
21.3.13 Line Status Register n (SCLSR)....................................................................... 1069
21.3.14 Serial Error Register n (SCRER)...................................................................... 1070
21.4 Operation......................................................................................................................... 1071
21.4.1 Overview.......................................................................................................... 1071
21.4.2 Operation in Asynchronous Mode.................................................................... 1074
21.4.3 Operation in Clocked Synchronous Mode........................................................1085
21.5 SCIF Interrupt Sources and the DMAC........................................................................... 1094
21.6 Usage Notes..................................................................................................................... 1096
Section 22 Serial I/O with FIFO (SIOF)......................................................................1099
22.1 Features............................................................................................................................1099
22.2 Input/Output Pins............................................................................................................. 1101
22.3 Register Descriptions....................................................................................................... 1102
22.3.1 Mode Register (SIMDR).................................................................................. 1104
22.3.2 Control Register (SICTR)................................................................................. 1106
22.3.3 Transmit Data Register (SITDR)...................................................................... 1108
22.3.4 Receive Data Register (SIRDR)....................................................................... 1109
22.3.5 Transmit Control Data Register (SITCR)......................................................... 1110
22.3.6 Receive Control Data Register (SIRCR).......................................................... 1111
22.3.7 Status Register (SISTR)....................................................................................1112
22.3.8 Interrupt Enable Register (SIIER).................................................................... 1118
22.3.9 FIFO Control Register (SIFCTR)..................................................................... 1120
22.3.10 Clock Select Register (SISCR)......................................................................... 1122
22.3.11 Transmit Data Assign Register (SITDAR)....................................................... 1123
22.3.12 Receive Data Assign Register (SIRDAR)........................................................ 1125
22.3.13 Control Data Assign Register (SICDAR)......................................................... 1126
22.4 Operation......................................................................................................................... 1128
22.4.1 Serial Clocks..................................................................................................... 1128
22.4.2 Serial Timing.................................................................................................... 1129
22.4.3 Transfer Data Format........................................................................................1131
22.4.4 Register Allocation of Transfer Data................................................................1133
22.4.5 Control Data Interface...................................................................................... 1135
22.4.6 FIFO..................................................................................................................1137
22.4.7 Transmit and Receive Procedures.....................................................................1139
22.4.8 Interrupts...........................................................................................................1144
22.4.9 Transmit and Receive Timing...........................................................................1146
Section 23 Serial Peripheral Interface (HSPI)............................................................1151
23.1 Features............................................................................................................................1151