10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 291 of 1658
REJ09B0261-0100
(8) Interrupt Mask Clear Register 0 (INTMSKCLR0) INTMSKCLR0 is a 32-bit write-only register that clears the mask settings for each of the interrupt requests IRQn (n = 0 to 7). Undefined values are read from this register.
161718192021222324252627282931 30
0000000000000000
IC07IC06
IC05IC04IC03IC02
IC00 IC01
RRRRRRRRR/WR/WR/WR/WR/WR/WR/W R/W
Bit:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
⎯⎯
RRRRRRRRRRRRRRRR
Bit:
Initial value:
R/W:
Bit Name
Initial
Value R/W Description
31 IC00 0 R/W Clears masking of IRQ0
interrupt.
30 IC01 0 R/W Clears masking of IRQ1
interrupt.
29 IC02 0 R/W Clears masking of IRQ2
interrupt.
28 IC03 0 R/W Clears masking of IRQ3
interrupt.
27 IC04 0 R/W Clears masking of IRQ4
interrupt.
26 IC05 0 R/W Clears masking of IRQ5
interrupt.
25 IC06 0 R/W Clears masking of IRQ6
interrupt.
24 IC07 0 R/W Clears masking of IRQ7
interrupt.
[When read]
Undefined values are
read.
[When written]
0: No effect
1: Clears the
corresponding interrupt
mask (enables the
interrupt)
23 to 0 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.