32. Electrical Characteristics

Rev.1.00 Jan. 10, 2008 Page 1580 of 1658

REJ09B0261-0100

D31 to D0
(Read)
(SA: IO memory)

Legend:

IO: DACK device
SA: Single-address DMA transfer
DA: Dual-address DMA transfer
Note: DACK is configured as active-high.
A25 to A5
A4 to A0
T1 T2TB2 TB1 TB2 TB1 TB2 TB1Twb Twb TwbTweTw
tAD
tCSD
tRSD
tRDH
tRDS
tBSD
tAD
tRDH
tRSD
tRDS
tAD
tCSD
tRDYH
tRDYS
tRDYH
tRDYS
tRDYH
tRDYS
tDACD tDACD
tDACD tDACD
tRWD tRWD
CLKOUT
CSn
RD/WR
BS
RDY
RD
DACKn
DACKn
(DA)
Figure 32.14 Burst ROM Bus Cycle (One Internal Wait Cycle + One External Wait Cycle for the 1st Datum; One Internal Wait Cycle for the 2nd, 3rd, and 4th Data)