Renesas SH7781 - page 318

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 288 of 1658
REJ09B0261-0100
Bit Name
Initial
Value R/W Description
26 IM010 0 R/W Masks the interrupt source
of IRL3 to IRL0 = LHLH
(H'5).
25 IM009 0 R/W Masks the interrupt source
of IRL3 to IRL0 = LHHL
(H'6).
24 IM008 0 R/W Masks the interrupt source
of IRL3 to IRL0 = LHHH
(H'7).
23 IM007 0 R/W Masks the interrupt source
of IRL3 to IRL0 = HLLL
(H'8).
22 IM006 0 R/W Masks the interrupt source
of IRL3 to IRL0 = HLLH
(H'9).
21 IM005 0 R/W Masks the interrupt source
of IRL3 to IRL0 = HLHL
(H'A).
[When read]
0: The interrupt is
accepted.
1: The interrupt is
masked.
[When written]
0: No effect
1: Masks the interrupt
20 IM004 0 R/W Masks the interrupt source
of IRL3 to IRL0 = HLHH
(H'B).
19 IM003 0 R/W Masks the interrupt source
of IRL3 to IRL0 = HHLL
(H'C).
18 IM002 0 R/W Masks the interrupt source
of IRL3 to IRL0 = HHLH
(H'D).
17 IM001 0 R/W Masks the interrupt source
of IRL3 to IRL0 = HHHL
(H'E).
16 — 0 R Reserved
This bit is always read as 0. The write value should
always be 0.