22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1111 of 1658
REJ09B0261-0100
22.3.6 Receive Control Data Register (SIRCR) SIRCR is a 32-bit readable/writable register that stores receive control data of the SIOF. The setting of SIRCR is valid only when bits FL3 to FL0 in SIMDR are set to 1xxx (x: any value).
161718192021222324252627282931 30
——
SIRC0[15:0]
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/W
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/W
BIt:
Initial value:
R/W:
01234567891011121315 14
——
SIRC1[15:0]
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 16 SIRC0[15:0] Undefined R/W Control Channel 0 Receive Data
These bits store data received from the SIOF_RXD pin
as control channel 0 receive data. The position of the
control channel 0 data in the transmit or receive frame
depends on the value set the CD0A bit in SICDAR.
These bits are valid when the CD0E bit in SICDAR
is set to 1.
15 to 0 SIRC1[15:0] Undefined R/W Control Channel 1 Receive Data
These bits store data received from the SIOF_RXD pin
as control channel 1 receive data. The position of the
control 1 channel data in the transmit or receive frame
depends on the value set in the CD1A bit in SICDAR.
These bits are valid when the CD1E bit in SICDAR
is set to 1.