Renesas SH7781 - page 502

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 472 of 1658
REJ09B0261-0100
Access Size Address
MDQ31 to
MDQ24
MDQ23 to
MDQ16
MDQ15 to
MDQ8
MDQ7 to
MDQ0
Word Address 0 Data
15 to 8
Data
7 to 0
Address 2 Data
15 to 8
Data
7 to 0
Address 4 Data
15 to 8
Data
7 to 0
Address 6 Data
15 to 8
Data
7 to 0
Longword Address 0 Data
31 to 24
Data
23 to 16
Data
15 to 8
Data
7 to 0
Address 4 Data
31 to 24
Data
23 to 16
Data
15 to 8
Data
7 to 0
Quadword Address 0
(First access:
Address 0)
Data
63 to 56
Data
55 to 48
Data
47 to 40
Data
39 to 32
Address 0
(Second access:
Address 4)
Data
31 to 24
Data
23 to 16
Data
15 to 8
Data
7 to 0