Appendix
Rev.1.00 Jan. 10, 2008 Page 1644 of 1658
REJ09B0261-0100
Pin Name
(LSI level)
Pin Name
(Module level) Module I/O When Not in Use
MCLK[1:0] MCLK[1:0] DBSC2 O Open
MCLK[1:0] MCLK[1:0] DBSC2 O Open
MDQS[3:0] MDQS[3:0] DBSC2 I/O Open
MDQS[3:0] MDQS[3:0] DBSC2 I/O Open
MDM[3:0] MDQ[3:0] DBSC2 O Open
MDQ[31:0] MDQ[31:0] DBSC2 I/O Open
MCKE MCKE DBSC2 O Open
MCAS MCAS DBSC2 O Open
MRAS MRAS DBSC2 O Open
MCS MCS DBSC2 O Open
MWE MWE DBSC2 O Open
MODT MODT DBSC2 O Open
MA[14:0] MA[14:0] DBSC2 O Open
MBA[2:0] MBA[2:0] DBSC2 O Open
MBKPRST MBKPRST DBSC2 I Pulled-up to VDD-DDR
AD[31:24] PCIC I/O
D[63:56] LBSC I/O
D[63:56]/
AD[31:24]
Port A[7:0] GPIO I/O
Open*2
AD[23:18] PCIC I/O
D[55:50] LBSC I/O
D[55:50]/
AD[23:18]
Port B[7:2] GPIO I/O
Open*2
AD[17:16] PCIC I/O
D[49:48] LBSC I/O
Open*2
DB[5:4] DU O
D[49:48]/
AD[17:16]/
DB[5:4]
Port B[1:0] GPIO I/O
Open*2
AD[15:12] PCIC I/O
D[47:44] LBSC I/O
D[47:44]/
AD[15:12]/
DB[3:0]
DB[3:0] DU O
Open*2