13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 552 of 1658
REJ09B0261-0100
Cache snoop functions are supported when the PCIC is a target (cache coherency can be
supported by sacrificing performance).
Supports four external interrupt inputs (INTA, INTB, INTC, and INTD) in host mode
Supports one external interrupt output (INTA) in normal mode
Both big endian and little endian are supported in SH7785 (the PCI bus operates in little
endian mode).
Note: The following PCI functions are not supported.
Supports cache (without the SBO and SDONE pins)
Address wraparound mechanism
PCI JTAG (this LSI supports JTAG)
Dual address cycles
Interrupt acknowledge cycles
Start of fast back-to-back transfer (it is supported when the PCIC operates as a target device)
Extended ROM for initialization, and boot of system