19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 853 of 1658
REJ09B0261-0100
19.3.4 Display Unit Status Register Clear Register (DSRCR) The display unit status register clear register (DSRCR) is a register which clears the various flags in DSSR.
R/W:
Internal update:
R/W:
Internal update:
161718192021222324252627282931 30Bit:
Initial value:
RRRRRRRRRRRRRRRR
0000000000000000
RRRRRRRRWWRWRRWW
00000000000——
HBCLRICL
VBCL
TVCL FRCL
01234567891011121315 14Bit:
Initial value:
Bit Bit Name
Initial
Value R/W
Internal
Update Description
31 to 16 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
15 TVCL Undefined W None TV Synchronous Signal Error Flag Clear
0: The TVR flag in DSSR is not changed.
1: The TVR flag in DSSR is cleared to 0.
14 FRCL Undefined W None Flame Flag Clear
0: The FRM flag in DSSR is not changed.
1: The FRM flag in DSSR is cleared to 0.
13, 12 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
11 VBCL Undefined W None Vertical Blanking Flag Clear
0: The VBK flag in DSSR is not changed.
1: The VBK flag in DSSR is cleared to 0.
10 0 R Reserved
This bit is always read as 0. The write value
should always be 0.