Renesas SH7781 Table 3.6 Logic Operation Instructions

3. Instruction Set
Rev.1.00 Jan. 10, 2008 Page 57 of 1658
REJ09B0261-0100
Instruction Operation Instruction Code Privileged T Bit New
MULU.W Rm,Rn Unsigned,
Rn × Rm → MACL
16 × 16 → 32 bits
0010nnnnmmmm1110 — — —
NEG Rm,Rn 0 – Rm → Rn 0110nnnnmmmm1011 — — —
NEGC Rm,Rn 0 – Rm – T → Rn,
borrow → T
0110nnnnmmmm1010 — Borrow —
SUB Rm,Rn Rn – Rm → Rn 0011nnnnmmmm1000 — — —
SUBC Rm,Rn Rn – Rm – T → Rn,
borrow → T
0011nnnnmmmm1010 — Borrow —
SUBV Rm,Rn Rn – Rm → Rn,
underflow → T
0011nnnnmmmm1011 — Underflow —
Table 3.6 Logic Operation Instructions
Instruction Operation Instruction Code Privileged T Bit New
AND Rm,Rn Rn & Rm → Rn 0010nnnnmmmm1001 — — —
AND #imm,R0 R0 & imm → R0 11001001iiiiiiii — — —
AND.B #imm, @(R0,GBR) (R0 + GBR) & imm
→ (R0 + GBR)
11001101iiiiiiii — — —
NOT Rm,Rn ~Rm → Rn 0110nnnnmmmm0111 — — —
OR Rm,Rn Rn | Rm → Rn 0010nnnnmmmm1011 — — —
OR #imm,R0 R0 | imm → R0 11001011iiiiiiii — — —
OR.B #imm, @(R0,GBR) (R0 + GBR) | imm
→ (R0 + GBR)
11001111iiiiiiii — — —
TAS.B @Rn When (Rn) = 0, 1 → T
Otherwise, 0 → T
In both cases,
1 → MSB of (Rn)
0100nnnn00011011 — Test
result
—
TST Rm,Rn Rn & Rm;
when result = 0, 1 → T
Otherwise, 0 → T
0010nnnnmmmm1000 — Test
result
—
TST #imm,R0 R0 & imm;
when result = 0, 1 → T
Otherwise, 0 → T
11001000iiiiiiii — Test
result
—
TST.B #imm, @(R0,GBR) (R0 + GBR) & imm;
when result = 0, 1 → T
Otherwise, 0 → T
11001100iiiiiiii — Test
result
—
XOR Rm,Rn Rn ∧ Rm → Rn 0010nnnnmmmm1010 — — —