Renesas SH7781 Table 29.2 Register Status in Each Processing State

29. User Break Controller (UBC)
Rev.1.00 Jan. 10, 2008 Page 1456 of 1658
REJ09B0261-0100
Table 29.2 Register Status in Each Processing State
Register Name Abbreviation Power-on Reset Manual Reset Sleep
Match condition setting
register 0
CBR0 H'20000000 Retained Retained
Match operation setting
register 0
CRR0 H'00002000 Retained Retained
Match address setting
register 0
CAR0 Undefined Retained Retained
Match address mask
setting register 0
CAMR0 Undefined Retained Retained
Match condition setting
register 1
CBR1 H'20000000 Retained Retained
Match operation setting
register 1
CRR1 H'00002000 Retained Retained
Match address setting
register 1
CAR1 Undefined Retained Retained
Match address mask
setting register 1
CAMR1 Undefined Retained Retained
Match data setting
register 1
CDR1 Undefined Retained Retained
Match data mask setting
register 1
CDMR1 Undefined Retained Retained
Execution count break
register 1
CETR1 Undefined Retained Retained
Channel match flag
register
CCMFR H'00000000 Retained Retained
Break control register CBCR H'00000000 Retained Retained
The access size must be the same as the control register size. If the size is different, the register is
not written to if attempted, and reading the register returns the undefined value. A desired break
may not occur between the time when the instruction for rewriting the control register is executed
and the time when the written value is actually reflected on the register. In order to confirm the
exact timing when the control register is updated, read the data which has been written most
recently. The subsequent instructions are valid for the most recently written register value.