19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 921 of 1658
REJ09B0261-0100
19.3.52 External Synchronization Control Register (ESCR) The external synchronization control register (ESCR) controls the dot clock.
R/W:
Internal update:
R/W:
Internal update:
161718192021222324252627282931 30Bit:
Initial value:
R/WRRRR/WRRRRRRRRRRR
0000000000000000
DCLK
DIS
DCLK
SEL
— —
R/WR/WR/WR/WR/WRRRRRRRRRRR
0000000000000000
FRQSEL
— —
01234567891011121315 14Bit:
Initial value:
Bit Bit Name
Initial
Value R/W
Internal
Update Description
31 to 21 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
20 DCLKSEL 0 R/W None DOTCLKIN Select
To enable this bit, the DCKE bit in DEFR should
be set to 1. In the initial state, this bit is fixed to 0.
0: The input dot clock source is the DCLKIN pin
1: The input dot clock is DUck
This setting should be made such that the
frequency of the frequency-divided dot clock
generated by the dot clock generation circuit is
50 MHz or lower.
19 to 17 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
16 DCLKDIS 0 R/W None DOTCLKOUT Disable
0: DOTCLKOUT is output.
1: DOTCLKOUT is not output.
DOTCLKOUT is fixed to low level.
15 to 5 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.