Renesas SH7781 32.3.14 MMCIF Module Signal Timing Table 32.19 MMCIF Module Signal Timing , Figure 32.56 MMCIF Transmission Timing

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1613 of 1658
REJ09B0261-0100
32.3.14 MMCIF Module Signal Timing
Table 32.19 MMCIF Module Signal Timing
Item Symbol Min. Max. Unit Figure
MMCCLK clock cycle time tMMcyc 50 — ns
MMCCLK clock high level width tMMWH 0.4 × tMmcyc — ns
MMCCLK clock low level width tMMWL 0.4 × tMMcyc — ns
MMCCMD output data delay time tMMTCD — 10 ns
32.56
MMCCMD input data hold time tMMRCS 10 — ns
MMCCMD input data setup time tMMRCH 10 — ns
32.57, 32.58
MMCD output data delay time tMMTDD — 10 ns 32.56
MMCD input data setup time tMMRDS 10 — ns 32.57, 32.58
MMCD input data hold time tMMRDH 10 — ns
Note: tMmcyc is the period of one MMCCLK cycle.
tMMcyc
tMMWH
tMMTDD tMMTDD
tMMTCD tMMTCD
tMMWL
MMCLK
MMCCMD (Output)
MMCDAT (Output)
Figure 32.56 MMCIF Transmission Timing