20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 1004 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
2 to 0 MC_CFS All 0 R Command pointer status display
000: MCCF command parameter 1 setting wait state
001: MCCF command parameter 2 setting wait state
010: MCCF command parameter 3 setting wait state
011: MCCF command parameter 4 setting wait state
100: MCCF command parameter 5 setting wait state
101: MCCF command parameter 6 setting wait state
110: MCCF command parameter 7 setting wait state
111: MCCF command parameter 8 setting wait state
20.3.23 MC Frame Width Setting Register (MCWR) MCWR is in the MC register block and sets the input frame width in pixel units.
161718192021222324252627282931 30
0000000000000000
⎯⎯
⎯⎯
BIt:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
MC_W⎯⎯
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W⎯⎯
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 12 All 0 Reserved
These bits are always read as 0. The write value should
always be 0.
11 to 0 MC_W All 0 R/W Frame width setting
Should be set by the number of pixels.
Notes: 1. MC processi ng is prohibited when the setting is 0.
2. Addition is performed taking that 1 pixel = 1 byte.
3. MCWR (bytes) + MCYPR (bytes) should be 16 bytes x n (n: an integer greater than 0)
4. MCWR (bytes)/2 + MCUVPR (bytes) should be 8 bytes x n (n: an integer greater than
0)
5. MCWR (bytes)/2: Shifts the MCWR setting one bit to the right. (When the setting is odd,
the bit 0 setting is discarded.)