Renesas SH7781 32.3.16 SSI Interface Module Signal Timing Table 32.21 SSI Interface Module Signal Timing , Figure 32.62 SSI Clock Input/Output Timing , Figure 32.63 SSI Transmission Timing (1)

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1616 of 1658
REJ09B0261-0100
32.3.16 SSI Interface Module Signal Timing
Table 32.21 SSI Interface Module Signal Timing
Item Symbol Min. Max. Unit Remarks Figure
Output cycle time tOSCK 40 710 ns Output
Input cycle time tISCK 80 3300 ns Input
Input high level width/input low level
width
tIHC/tILC 30 ns Input 32.62
Output high level width/output low level
width
TOHC/tOLC 13 ns Output
SCK output rise time tRC — 60 ns Output
SDATA output delay time tDTR — 50 ns Transmit 32.63,
32.64
SDATA/WS input setup time tSR 10 — ns Receive
SDATA/WS input hold time tHTR 10 — ns Receive
32.65,
32.66
t
OHC
t
IHC
t
RC
V
IH
V
OH
V
IH
V
OH
V
IL
V
OH
t
OLC
t
ISCK
t
OSCK
t
ILC
SSIn_SCK
V
IH
V
OH
V
IH
V
OH
V
IL
V
OH
Figure 32.62 SSI Clock Input/Output Timing
t
DTR
t
HTR
SSIn_SCKn
SSIn_WS
SSIn_SDATA
Figure 32.63 SSI Transmission Timing (1)