14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 693 of 1658
REJ09B0261-0100
14.3.9 DMA Extended Resource Selectors 0 to 5 (DMARS0 to DMARS5)
DMARS are 16-bit readable/writable registers. DMARS0, DMARS1, DMARS2, DMARS3,
DMARS4, and DMARS5 specify DMA transfer request source from peripheral modules for
channels 0 and 1, channels 2 and 3, channels 4 and 5, channels 6 and 7, channels 8 and 9, and
channels 10 and 11 respectively. These registers can specify the transfer request of SCIF0 to
SCIF5, HAC0, HAC1, HSPI, SIOF, SSI0, SSI1, FLCTL, and MMCIF.
When MID/RID other than the values listed in table 14.3 is specified, the operation of this LSI is
not guaranteed. The transfer request from DMARS is valid only when the resource select bits RS3
to RS0 have been set to B'1000 for CHCR. When the bits are not set to B'1000, transfer request
source is not accepted even if DMARS has been specified.
• DMARS0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
Ch1MID Ch1RID Ch0MID Ch0RID
• DMARS1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
Ch3MID Ch3RID Ch2MID Ch2RID
• DMARS2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
Ch5MID Ch5RID Ch4MID Ch4RID
• DMARS3
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
Ch7MID Ch7RID Ch6MID Ch6RID