32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1601 of 1658
REJ09B0261-0100
t
PCISU
0.4V
DDQ
PCICLK
Input
0.4V
DDQ
t
PCIH
Figure 32.39 PCI Input Signal Timing 32.3.7 DMAC Module Signal Timing Table 32.12 DMAC Module Signal Timing Conditions: VDDQ= 3.0 to 3.6 V, VDD= 1.5 V, Ta= 40 to 85°C, CL= 30 pF, PLL2 on
Module Item Symbol Min. Max. Unit Figure Remarks
DMAC DREQ setup time tDRQS 2.5 — ns 32.40
DREQ hold time tDRQH 1.5 —
DRAK delay time tDRAKD 1.5 6
DACK delay time tDAKD 1.5 6
t
DRQS
CLKOUT
DRAK
DREQ
t
DRQH
t
DRAKD
t
DRAKD
Figure 32.40 DREQ/DRAK Signal Timing