27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1353 of 1658
REJ09B0261-0100
27.3.7 Data Register (FLDATAR) FLDATAR is a 32-bit readable/writable register. It stores data to be input or output used when the CDSRC bit in FLCMDCR is cleared to 0 in command access mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
DT[31:24] DT[23:16]
DT[15:8] DT[7:0]
Bit Bit Name
Initial
Value R/W Description
31 to 24 DT[31:24] H'00 R/W Fourth Data
Specify the 4th data to be input or output via the FD7 to
FD0 pins.
In writing: Specify write data
In reading: Store read data
23 to 16 DT[23:16] H'00 R/W Third Data
Specify the 3rd data to be input or output via the FD7 to
FD0 pins.
In writing: Specify write data
In reading: Store read data
15 to 8 DT[15:8] H'00 R/W Second Data
Specify the 2nd data to be input or output via the FD7
to FD0 pins.
In writing: Specify write data
In reading: Store read data
7 to 0 DT[7:0] H'00 R/W First Data
Specify the 1st data to be input or output via the FD7 to
FD0 pins.
In writing: Specify write data
In reading: Store read data