Renesas SH7781 - page 190

7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 160 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
31 to 14 ⎯ All 0 R Reserved
For details on reading/writing these bits, see General
Precautions on Handling of Product.
13 to 8 EPR Undefined R/W
7 to 4 ESZ Undefined R/W
Page Control Information
Each bit has the same function as the corresponding
bit of the unified TLB (UTLB). For details, see section
7.4, TLB Functions (TLB Extended Mode; MMUCR.ME
= 1)
3 to 0 ⎯ All 0 R Reserved
For details on reading/writing these bits, see General
Precautions on Handling of Product.
7.2.7 Physical Address Space Control Register (PASCR)
PASCR controls the operation in the physical address space.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit:
00000000
000000
00000000
Initial value:
RRRRRRRRRRRRRRRR
R/W
UB
R/W R/W R/W R/W R/W R/W R/W
R/W:
Bit:
Initial value:
R/W:
1514131211109876543210
00 000000 00
RRRRRRRR