32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1592 of 1658
REJ09B0261-0100
32.3.4 DBSC2 Signal Timing Table 32.9 DBSC2 Signal Timing Conditions: VDD-DDR= 1.7 to 1.9 V, Vref= 0.9 V, VDD= 1.1 V, Ta= 20 to +85/40 to 85°C, CL= 30 pF, ODT=on), Drive Strength=Normal
Item Symbol Min. Max. Unit Figure Notes
MCK output cycle tCK 3.33 5.0 ns
MCK output high-level pulse
width
tCH 0.45 0.55 tMCK
MCK output low-level pulse
width
tCL 0.45 0.55 tMCK
880 — ps DDR2-600 Address and control signal
setup time to MCK rising edge
tIS
1290 DDR2-400
880 — ps DDR2-600 Address and control signal hold
time to MCK rising edge
tIH
1290 DDR2-400
Address and control signal
width
tIPW 0.6 tMCK
MCLK-to-MDQS skew time
(Read)
tRDQSDLY 0.2 1.4 ns
MDQS high-level pulse width
(Read)
tRDQSH 0.35 0.65 tMCK
MDQS low-level pulse width
(Read)
tRDQSL 0.35 0.65 tMCK
MDQS preamble (Read) tRPRE 0.9 1.1 tMCK
MDQS postamble (Read) tRPST 0.4 0.6 tMCK
390 390 DDR2-600 MDQS-to-MDQ skew time
(Read)
tRDQSQ
590 590
ps
DDR2-400
MDQ signal hold time to DQS
(Read)
tRQH 0.45 × tMCK
470
— ps DDR2-600
0.45 × tMCK
630
DDR2-400