10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 292 of 1658
REJ09B0261-0100
(9) Interrupt Mask Clear Register 1 (INTMSKCLR1) INTMSKCLR1 is a 32-bit write-only register that clears the mask settings for the IRL interrupt requests. Undefined values are read from this register.
161718192021222324252627282931 30
0000000000000000
IC10 IC11
RRRRRRRRRRRRRRR/W R/W
Bit:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
⎯⎯
RRRRRRRRRRRRRRRR
Bit:
Initial value:
R/W:
Bit Name
Initial
Value R/W Description
31 IC10 0 R/W Clears masking of IRL3 to
IRL0 interrupt sources
when IRL3 to IRL0 operate
as an encoded interrupt
input.
30 IC11 0 R/W Clears masking of IRL7 to
IRL4 interrupt sources
when IRL7 to IRL4 operate
as an encoded interrupt
input.
[When read]
Undefined values are read.
[When written]
0: No effect
1: Clears the
corresponding interrupt
mask (enables the
interrupt)
29 to 0 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.